Field of the Invention
The present invention relates to a method of manufacturing a lead frame and an integrated circuit package having a structure with pins of a very large number in which the above lead frame is bonded to a semiconductor chip.
Description of the Related Art
The present invention relates to a semiconductor device having a structure with pins of the very large number obtained by joining a new lead frame to a semiconductor chip, and a method of manufacturing the semiconductor device.
Description of the Related Art
FIG. 1 is a cross-sectional view showing a semiconductor device, i.e., an integrated circuit package in which a semiconductor chip can be connected to a circuit board or the like through an organic substrate having a projecting electrode such as a solder ball.
In FIG. 1, an organic multilayer circuit board a having about two to six layers formed of an organic material is mounted on its surface with a semiconductor chip b. An electrode of the semiconductor chip b and a wiring film c formed on the surface of the organic multilayer circuit board a are connected to each other by wire bonding employing metal wires d or the like.
A solder ball e is provided on a rear surface of the organic multilayer circuit board a and serves as a projecting electrode electrically connected through a through hole i to the wiring film c on the surface of the organic multilayer circuit board a. The solder ball e is faced to the outside through an opening of a solder resist film f. The semiconductor chip b together with the metal wire d are sealed by a sealing resin g.
An integrated circuit package j is formed such that the solder balls e formed on the rear surface of the organic multilayer circuit board a is connected to a circuit board h. Being provided with a large number of solder balls e arranged in a grid fashion, the organic multilayer circuit board a is often called a ball grid array (BGA). The integrated circuit package j employing the organic multilayer circuit board a is called a BGA package.
The BGA package j employs the wire bonding to connect the electrode of the semiconductor chip b with the wiring film c of the organic multilayer circuit board a. Therefore, this arrangement limits reduction of a pitch between electrode pads of the semiconductor chip b.
Moreover, since a processing for forming the projecting electrodes e of the organic multilayer circuit board a employs a method of physically locating the so-called solder balls, the processing encounters the following problems.
1) When the solder balls e are set at predetermined positions, they are easily displaced therefrom.
2) Since the sizes of the solder balls e are selected by using a sieve or a mesh, the sizes thereof tends to be uneven.
3) There is a limit in achievement of a more minute arrangement pitch between the solder balls e.
4) Since a base of the organic multilayer circuit board a is formed of an insulative substrate, the solder balls e cannot be formed by electroplating which allows the sizes of the solder balls e to be uniform in size and allows pitches therebetween to be more minute.
5) Composition of the soft solder ball is restricted.
The assignee of the present invention proposed an integrated circuit package having a structure with pins of a very large number obtained by jointing a new lead frame to a semiconductor chip. A method of manufacturing the above integrated circuit package is disclosed in an application filed by the same assignee (U.S. Ser. No. 08/561,245 filed on Nov. 21, 1995). The integrated circuit package is manufactured as follows. Specifically, a large number of leads are formed on a surface of a metal base by copper electrolytic plating. An insulative film for holding each of the leads is formed at portions other than an inner lead portion. A solder resist film is further formed. A projecting electrode is formed by electrolytic plating at an end portion of an outer lead portion of each of the leads. Then, the metal base is selectively removed except its outer peripheral joint portion, thereby a lead frame having each of the lead portions separately formed is achieved. A semiconductor chip is joined to an inner lead frame portion of the lead frame. Then, a reinforcement board is bonded to a rear surface of the outer lead portion of the lead frame. The semiconductor chip is sealed with resin. Then, the lead frame is cut at its joint portions to obtain the lead frame. A large number of projecting electrodes are formed in a grid fashion at a peripheral portion around the semiconductor chip.
According to this integrated circuit package, since the metal base is employed and the leads and the projecting electrodes are formed by electroplating, the leads can be formed in a finer pattern and the projecting electrodes can be prevented from being displaced. Moreover, the size of each of the projecting electrodes can be made uniform and the finer pitches therebetween can be achieved, which enables a large-scale integrated circuit (LSI) to be more downsized and to have pins of the very large number.
As shown in FIG. 2, a metal base 1 includes a substrate 2 made of copper or copper alloy, an aluminum film 3 serving as an etching barrier or stopper film, and a thin copper film 4 serving as a ground for copper plating. The substrate 2, the aluminum film 3 and the thin copper film 4 are laminated successively.
When the metal base 1 is selectively etched, the copper substrate 2 is initially etched, the aluminum film 3 is successively etched, and then the thin copper film 4 is etched, thereby copper leads being separated. Therefore, the metal base 1 may encounter the following problems.
(i) In a process of etching the thin copper film 4, the copper lead is also etched and consequently has a small line width and a small thickness of its inner lead portion in a fine pattern as compared with their standards. As shown in FIGS. 3A and 3B which are photographs for evaluation, when the metal base 1 is etched to form the leads at a pitch of 70 .mu.m (a standard lead width of 40 .mu.m and standard pitch between the leads of 30 .mu.m), a line width of an inner lead portion of the lead becomes smaller than the standard. Specifically, the lead satisfying the standard is hardly obtained. PA0 (ii) Since the leads are formed in a fine pattern, the copper film 4 which is not removed by etching tends to remain between the adjacent inner lead portions, thereby short-circuiting the adjacent inner lead portions. PA0 (iii) When the copper film 4 is etched, study of FIGS. 3A and 3B which are photographs for evaluation reveals that a work control margin is very narrow. Specifically, if an etching time is even a little longer, then the lead becomes narrow in the line width, and if the etching time is too short, there remains the copper film 4 which is not removed by etching. PA0 (iv) Since the ground copper film 4 and the copper lead have the same color, the over-etching tends to be carried out when the copper film 4 is etched. PA0 (v) The thickness of the ground copper film 4 must be set to 1 to 2 .mu.m, thereby the etching condition being severe.